1. Field of the Invention
The present invention relates to a display apparatus and a method of laying out pixel circuits to a panel-type display apparatus, and a method of laying out pixel circuits in such a panel-type display apparatus.
2. Description of the Related Art
Recently in the field of display apparatus, panel-type display apparatus such as LCD (Liquid Crystal Display) panels, EL (Electro Luminescence) display panels, PDPs (Plasma Display Panels), etc. has been becoming the mainstream, replacing existing CRT (Cathode-Ray Tube) display apparatus because of their thin, lightweight, and high-definition properties.
Of the panel-type display apparatus, active-matrix display apparatus incorporating active elements in pixel circuits which include electrooptical elements are capable of giving high functionality to the pixel circuits as the pixel circuits may be constructed of TFTs (Thin Film Transistors).
Generally, active-matrix display apparatus with TFT pixel circuits include correcting circuits combined with the pixel circuits, respectively, for correcting variations of TFT characteristics such as threshold voltages Vth. See, for example, Japanese Patent Laid-open No. 2005-345722.
The correcting circuits combined with the pixel circuits, however, tend to increase the number of power supply lines for supplying a power supply voltage to the pixel circuits. The increased number of power supply lines poses a limitation on the area of the layout of pixels, which presents an obstacle to efforts for achieving a higher definition display capability by employing more pixels in the display apparatus.
It has been attempted to place a power supply line between two adjacent pixel circuits that are laid out symmetrically with respect to the power supply line to share the power supply line. The area of the layout of the pixel circuits is thus reduced for a higher definition display capability. See, for example, Japanese Patent Laid-open No. 2005-108528.
If transistors that make up pixel circuits are N-channel MOS transistors, then it is the general practice to employ a low-concentration source/drain structure such as an LDD (Lightly Doped Drain) structure, a DDD (Double Diffused Drain) structure, a GDD (Graded Doped Drain) structure, or an offset gate structure for relaxing a drain electric field to increase the withstand voltage and reducing a leakage. See, for example, Japanese Patent Laid-open No. 2000-208774. Details of the LDD structure will be described below. The other structures may also be similarly analyzed.
With the LDD structure, the N-channel MOS transistor can essentially be considered to be an equivalent to a transistor with resistors connected respectively to the source and the drain thereof. According to an example, the LDD region is determined by patterning a resist in the shape of a gate, and the source/drain region is determined by patterning a resist with a source/drain forming resist mask. See, for example, Japanese Patent Laid-open No. 2001-291870.
When a transistor having the LDD structure is fabricated, since the LDD region and the source/drain region are formed by respective independent processes, it is predicted that the lengths of these regions will vary independently of each other. Actually, if the length of the LDD region varies and becomes greater than a prescribed length, then the LDD region will have a resistance value greater than a prescribed value. If the length of the LDD region becomes smaller than the prescribed length, then the resistance value of the LDD region will be smaller than the prescribed value.
As shown in FIG. 10 of the accompanying drawings, if the LDD region on the drain side becomes longer (the resistance value thereof becomes greater), then the LDD region on the source side becomes shorter (the resistance value thereof becomes smaller). Conversely, if the LDD region on the drain side becomes shorter (the resistance value thereof becomes smaller), then the LDD region on the source side becomes longer (the resistance value thereof becomes greater).
With a view to reducing the area of the layout of pixel circuits, it is proposed, as shown in FIG. 11 of the accompanying drawings, to lay out two pixel circuits 200A, 200B symmetrically with respect to a power supply line 100.
For laying out the two pixel circuits 200A, 200B symmetrically, a layout structure may be considered to have drive transistors (TFTs) 202A, 202B for driving electrooptical elements 201A, 201B arranged such that drain regions (D) are positioned closely to the power supply line 100 and source regions (S) remotely from the power supply line 100, i.e., a line P interconnecting the drain regions (D) and the source regions (S) extends parallel to the direction of the array of the two pixel circuits 200A, 200B (the direction of pixel rows).
When the positional relationship between the LDD structures and the channels suffers variations in the above layout structure, since the variations are in the same direction with respect to the two drive transistors 202A, 202B, if the LDD region on the drain side of the drive transistor 202A becomes longer and the LDD region on the source side thereof becomes shorter, then the LDD region on the drain side of the drive transistor 202B becomes shorter and the LDD region on the source side thereof becomes longer.
As the LDD regions are thus shifted due to the variations in the positional relationship between the LDD structures and the channels, the resistance values of the LDD regions differ on the drain side and the source side. If the different resistance values are opposite to each other between the two drive transistors 202A, 202B, then the transistor characteristics TFT characteristics of the drive transistors 202A, 202B suffer variations. The pixel-to-pixel variations of the transistor characteristics due to the shifts of the LDD regions are characteristic variations that cannot be corrected by the above correcting circuits.
Though the problems of transistors having the LDD structure have been described above, the problems are not limited to such transistors having the LDD structure, but also hold true for all transistors having low-concentration source/drain regions such as transistors having the DDD structure and the GDD structure, and transistors having offset regions of the offset gate structure.